hubFS: THE place for F#

HDFS is a library written in F# which allows hardware to be designed, simulated and then implemented (using standard design flows via Verilog or VHDL) in FPGA's or ASIC's.

http://www.evilkid.pwp.blueyonder.co.uk/

• Digital logic circuit design in F#
• Structural and behavioural design styles
• VHDL and Verilog netlist generation
• Memory inference
• Instantiation of external HDL models
• Integrated simulator
• Verilog co-simulation (Modelsim only at the moment)
• C, C++ and C# simulation generation
• Integrated waveform viewer
• Resource reporting
• Tree based hierarchy viewer
• Small, but growing, library of utility circuits and functions
  

The library is based upon a project called HDCaml, authored by Tom Hawkins.  For more information on HDCaml see:

http://www.confluent.org/wiki/doku.php

Very cool!  I was looking at your "Future Plans" page and saw you were having performance problems and think that your blaming of exception use is correct.  CLR exceptions seem to be much heavier weight than OCaml exceptions and probably shouldn't be used as a normal flow-of-control device.

I look forward to playing around with this.

Lewis

Version 0.2

• The project has moved home.  Since I had to change my ISP I needed to rehouse HDFS.  I decided to host it on google code and start a related google group.
•   http://code.google.com/p/hdfs/
•   http://groups.google.com/group/hdfsharp
• Revised circuit design API.  Where possible standard operators are used and overloaded to allow integer and string arguments.
• Improved simulator which should fix the bugs in V0.1 and adds a few extra optimisations.  Completely redesigned API makes it much nicer to work with.
• Basic constant propogation optimisations applied automatically as circuits are built.
• Fixed point data type. 
  
• A few new library circuits.
• HDCaml compatibility API.
• The beginnings of a synthesizer for Xilinx FPGAs.  Although not complete, to me it's quite remarkable what a few hundred lines of ML can achieve.  Main things still to do:
•   Memory generation (distributed and block ram).
•   Hard multiplier support.
•   Fix buggy instantiation code.
•   EDIF generator (trying to reverse engineer EDIF is about as much fun as pulling out your own teeth...).
• Matlab Simulink model generator, kindly provided by John White.